電波の届きにくい倉庫・訪問診療・工場でも0.1秒で動くモバイル基盤：
〜「カメラで撮るだけ・3秒話すだけ」で完結する Flutter × Rust × 暗号化金庫〜

#![no_std]
#![forbid(unsafe_code)]

/// 64-bit packed Hybrid Logical Clock: [48-bit physical_ms | 16-bit logical_counter]
#[repr(transparent)]
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Debug)]
pub struct PackedHlc64(pub u64);

impl PackedHlc64 {
    #[inline]
    pub const fn new(physical_ms: u64, logical: u16) -> Self {
        Self(((physical_ms & 0xFFFF_FFFF_FFFF) << 16) | (logical as u64))
    }

    #[inline]
    pub const fn physical_ms(self) -> u64 {
        self.0 >> 16
    }

    #[inline]
    pub const fn logical(self) -> u16 {
        (self.0 & 0xFFFF) as u16
    }

    /// Local event tick: advances monotonically even if wall clock regresses.
    pub const fn tick_local(self, wall_ms: u64) -> Self {
        let old_l = self.physical_ms();
        if wall_ms > old_l {
            Self::new(wall_ms, 0)
        } else {
            Self::new(old_l, self.logical().saturating_add(1))
        }
    }

    /// Receive remote message HLC: enforces causal ordering e -> f => HLC(e) < HLC(f).
    pub const fn update_remote(self, remote: Self, wall_ms: u64) -> Self {
        let l_self = self.physical_ms();
        let l_rem = remote.physical_ms();
        let max_l = if wall_ms >= l_self && wall_ms >= l_rem {
            wall_ms
        } else if l_self >= l_rem {
            l_self
        } else {
            l_rem
        };

        let next_c = if max_l == l_self && max_l == l_rem {
            let m = if self.logical() >= remote.logical() { self.logical() } else { remote.logical() };
            m.saturating_add(1)
        } else if max_l == l_self {
            self.logical().saturating_add(1)
        } else if max_l == l_rem {
            remote.logical().saturating_add(1)
        } else {
            0
        };
        Self::new(max_l, next_c)
    }
}

/// Join-Semilattice LWW-Register CRDT with deterministic (HLC, NodeId) total order.
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub struct LwwRegister<T: Copy + PartialEq + Eq> {
    pub value: T,
    pub hlc: PackedHlc64,
    pub node_id: u32,
}

impl<T: Copy + PartialEq + Eq> LwwRegister<T> {
    /// Least Upper Bound (Join operator `sqcup`): associative, commutative, idempotent.
    #[inline]
    pub const fn merge(self, other: Self) -> Self {
        if self.hlc.0 > other.hlc.0 {
            self
        } else if self.hlc.0 < other.hlc.0 {
            other
        } else if self.node_id >= other.node_id {
            self
        } else {
            other
        }
    }
}